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.1. Field of the Invention
The present invention relates to a semiconductor device in which a semiconductor chip is incorporated, and a method of manufacturing the semiconductor device.
2. Description of the Related Art
A technique for achieving high-density wiring has been under development. A part of wiring is formed on a semiconductor chip in a multilayer structure. In this case, the wiring is electrically connected to an external terminal through a contact hole formed in an interlayer insulating film formed on the semiconductor chip. A flat bottom portion of the contact hole is formed in a planar shape in order to connect a wiring in the upper layer and the external terminal in one contact hole. However, as the dimensions of semiconductor devices become smaller, a focus margin of a focused ion beam is reduced and it becomes increasingly difficult to form a contact hole having a flat bottom portion.
The flat bottom portion of the contact hole may be formed by a self-alignment technique as disclosed in U.S. Pat. No. 5,919,981. In this technique, a silicon film formed on a semiconductor chip and a polysilicon layer for a contact hole are oxidized by dry etching. As a result, an oxide film is formed only in a region of the silicon film that is exposed, but the polysilicon layer is etched. An oxide film formed on the silicon film by oxidizing the silicon film is removed and, hence, a bottom portion of the contact hole is formed in a planar shape. In this technique, a film formed on the polysilicon layer for the contact hole is in-situ oxidized to prevent the polysilicon layer from being etched.
However, the oxide film formed on the silicon film is removed after the polysilicon layer is removed, and the film may be mixed into the polysilicon layer. The polysilicon layer is etched by dry etching or wet etching after being mixed with the oxide film. This may damage the silicon film and also may reduce a flatness of the bottom portion of the contact hole.
A technique for reducing the damage of the silicon film and for maintaining a flatness of the bottom portion of the contact hole is disclosed in Japanese Laid-Open Patent Application
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